1. Field of the Invention
The present invention relates to a sense amplifier circuit in a flash memory device and, in particular, to a sense amplifier circuit in a flash memory device to which an auxiliary cell array is connected to an input terminal of the sense amplifier to prevent a variation in a cell current according to a change of the position of source contact at the time of read-out operation.
2. Information Disclosure Statement
In general, a flash memory device performs a program operation, an erasure operation and a read-out operation. Data stored in a memory cell by a program operation is output by a read-out operation. The read-out operation is a process of comparing amounts of currents flowing through a reference cell and a memory cell by using a sense amplifier after making currents flow through the reference cell and a selected memory cell and outputting data output from the sense amplifier to a data output buffer. At this time, in case the amount of current flowing through the reference cell is larger than that flowing through the selected memory cell, it is decided that data of "1" is stored in the selected memory cell, and in case the amount of current flowing through the reference cell is smaller than that flowing through the selected memory cell, it is decided that data of "0" is stored in the selected memory cell. The sense amplifier circuit of a flash memory device used in read-out operation will be described below with reference to FIGS. 1 to 3.
FIG. 1 is a circuit diagram to illustrate the sense amplifier circuit of conventional flash memory device and FIG. 2 is a circuit diagram to illustrate a memory cell array of a flash memory device.
A load resistor R1 is connected between a source voltage Vcc and a node K1, and a reference cell C.sub.REF to which the source voltage Vcc is supplied through a control gate thereof is connected between the node K1 and the ground Vss. A load resistor R2 is connected between the source voltage Vcc and a node K2, and the node K2 is connected to a bit line of a main memory cell array 11. In addition, the nodes K1 and K2 are connected to a negative(-) input terminal and a positive(+) input terminal of a sense amplifier 12, respectively, and data is output through an output terminal OUT of the sense amplifier 12.
The main memory cell array 11 is constructed in such a way that a plurality of memory cells C1 to Cn are connected between a plurality of word lines WLO to WLn and a plurality of bit lines BLO to BLn, respectively, as shown in FIG. 2, wherein a source of each memory cell is composed of a junction to which impurity ions are implanted, that is, a local source line SL. At this time, since the local source line SL is formed of the junction into which the impurity ions are implanted, a resistance value of the local source line SL is large. Therefore, to reduce the resistance value, the local source line SL is connected to a common source line Sc composed of metal. The local source line SL is connected to the common source line Sc through a contact hole A formed at a constant spacing.
At the time of read-out operation, when one memory cell among the main memory cell array 11 is selected and the sense amplifier circuit is enabled, the source voltage Vcc is supplied to the sense amplifier circuit. Accordingly, a current path is formed through the load resistor R1 and reference cell C.sub.REF. Taking the amount of current flowing through the reference cell C.sub.REF, the voltage V.sub.1 applied to the node K1 becomes Vcc-I.sub.1 .times.R. At the same time, other current path is formed through the load resistor R2 and the selected memory cell of the main memory cell array 11, and at this time, a flow of current I.sub.2 through the load resistor R.sub.2 is generated and the voltage V.sub.2 is applied to the node K2. Then the sense amplifier 12 compares the voltage V.sub.1 of the node K1 according to the amount of current I.sub.1 flowing through the reference cell C.sub.REF and the volgate V.sub.2 of the node K2 according to the amount of current I.sub.2 flowing through the selected memory cell of the main memory cell array 11, and decides that data of "1" is stored, that is, the selected memory cell is a programmed cell, in case the voltage V.sub.1 is higher than the voltage V.sub.2, and that data of "0" is stored, that is, the selected memory cell is an erased cell, in case the voltage V.sub.1 is lower than the voltage V.sub.2, and accordingly outputs data through the output terminal OUT.
Since each source of the memory cell of the main memory cell array 11 is connected to the common source line Sc through the contact hole A, the distance from each source to the common source line Sc varies for each source and the resistance value of the common source line Sc varies at the time of read-out operation according to the position of each memory cell. That is, since the amount of current I.sub.2 varies according to the position of the selected memory cell, a uniform read-out operation is not performed.
For example, the resistance value of the common source line Sc in case the memory cell C1 positioned near to the contact hole A is selected is smaller than that in case the memory cell Cn positioned far from the contact hole A is selected, and the difference in the amount of current due to the difference in the resistance value is shown in FIG. 3. The curve Ic1 shown in FIG. 3 presents the amount of current flowing through the memory cell when the memory cell positioned far from the contact hole A is selected, and the curve Icn shown in FIG. 3 presents the amount of current flowing through the memory cell when the memory cell positioned near to the contact hole A is selected.
As can be seen from FIG. 3, since the current flowing through the memory cell, that is, the cell current varies according to the position of memory cell selected at the time of read-out operation, in case of using the conventional sense amplifier circuit, the precise readout of data stored in the memory cell is difficult and accordingly the reliability of the device is degraded.